1. Field of the Invention
The present disclosure relates to integrated circuits and, more particularly, to time-delay circuits.
2. Description of the Related Art
In the design of integrated circuits there is often felt the need for generating digital signals that are retarded with respect to an edge of a digital input signal and to determine the time delay in an analog manner.
In prior art there are known circuits that respond to a predetermined edge of a binary digital input signal, i.e. to a transition from one of the predetermined binary logic states to the other, with a delay Δt that is a function of the ratio between a capacitance C and a current I. A time-delay circuit of this type in which the transition from 1 to 0 is retarded is schematically illustrated in FIG. 1; it comprises a capacitor C1 connected to the input of an inverter INV1 and means for controlling the charge of the capacitor. These means comprise a controlled electronic switch in the form of an N-channel MOS transistor, indicated by M1, and a constant current generator G1 that are connected, in series with each other, between the terminals (VDD and ground) of a voltage supply source. More particularly, transistor M1 has its source terminal connected to ground and its drain terminal, i.e. the node A in the figure, connected to the generator G1. The input terminal IN and the output terminal OUT of the time-delay circuit are, respectively, the gate terminal of the transistor M1 and the output terminal of the inverter INV1.
Also known is the dual circuit of the one shown in FIG. 1, namely a circuit that utilizes a P-channel MOS transistor having its source terminal connected to the positive terminal VDD of the supply source and its drain terminal connected, via a constant current generator, to the negative terminal of the supply source and, via a capacitor, to the positive terminal of the supply source.
As far as the biasing of the capacitor is concerned, the terminal opposite to the one connected to the inverter input can be maintained at any desired potential.
A likewise known variant of the time-delay circuit of FIG. 1 is shown in FIG. 7. In this circuit the constant current generator G1 is substituted by a resistor R1, so that the time delay is a function of the product of the resistance of the resistor R1 multiplied by the capacitance of the capacitor C1.
Referring to FIG. 2, let us consider as input signal IN of the circuit of FIG. 1 a clock signal, i.e. a periodic succession of voltage pulses that vary in steps between a low value, ground potential for example (binary state 0), and a given positive voltage, VDD for example (binary state 1). When IN=1, the transistor M1 is conducting, so that the connection node A between the drain terminal of M1 and the generator G1 is substantially at ground potential (binary state 0), the capacitor C1 is discharged and, due to the effect of the inverter INV1, the output OUT of the delay circuit is a positive voltage, typically the supply voltage VDD. When the input signal IN passes from 1 to 0, the transistor M1 stops conducting and the capacitor C1 commences charging through the generator G1. When the voltage on the node A reaches the threshold voltage that makes the inverter switch, the output OUT of the time-delay circuit passes from the voltage VDD to ground potential. The time Δt1 that elapses between the moment the trailing edge of the signal IN changes from 1 to 0 and the switching of the inverter, i.e. the delay time of the circuit, obviously depends not only on the current I of the generator G1 and the capacitance of the capacitor C1, but also on the threshold voltage of the inverter INV1. The inverter is typically constituted by two complementary MOS transistors (i.e. an N-channel transistor and a P-channel transistor) that have a common drain terminal, while their source terminals are connected, respectively, to the ground terminal and the positive terminal VDD of the supply source. In this case the threshold voltage depends on the supply voltage VDD, the threshold voltages of the transistors and the mobility of the charge carriers (electrons and vacancies) of the transistors. The supply voltage VDD may be fixed with a good degree of precision (+/−1%) at a nominal value established in the design phase, but the threshold voltages of the transistors and the mobility of the charge carriers cannot be accurately fixed, because they depend on manufacturing parameters, which may vary within relatively wide limits, and depend also on the operating temperature, which—in its turn—depends on the operating conditions of the device in which the time-delay circuit is integrated. According to the prior art, if these difficulties are to be at least partially avoided, the designer has to adopt some rather complex measures that, for this very reason, go to the detriment of the simplicity of the circuit and occupy a not by any means negligible area of the integrated circuit.